80386 Microprocessor Datasheet.pdf _VERIFIED_
the i860 requires a one- to two-digit start address to find instructions in the data cache. the i860 likewise has one- to two-digit absolute and negative-offset addresses for the data cache and branch tables. this means that it is possible to perform conditional branch instructions while processing the program, and a conditional branch may be executed while processing another instruction. (there is a performance penalty for conditional branch instructions, so the i860 is unlikely to be competitive with an x86 microprocessor. fortunately, it is good enough to permit applications that need an embedded microprocessor to be able to work on the desktop, so it may be that this chip will be used in an embedded situation in the future.
80386 Microprocessor Datasheet.pdf
aside from the 16-bit width, many of the choices made by intel in the design of the i860 were motivated by money. the idea of being able to easily emulate the x86 architecture (and therefore run their legacy software) is a potentially lucrative one for intel. to make this happen, they felt it was important to construct the chip so that it could easily be duplicated with standard tools.
there is a small address gap between the floating point and integer caches in the i860. this is deliberate to allow the processor to execute the sparcv9 instructions with a single-byte base offset, which makes it easy to intermix floating-point and integer instructions in a program.
the instruction fetch, decode, and execute units may execute 16, 32, or 64 instructions per clock. each instruction has a data-processing unit, which decodes the instruction and schedules the next instruction in the pipeline. each instruction also includes a branch and link unit, which determines where to branch from and where to return when that branch is taken. this can perform the function of branch, branch/link, branch/link, branch/link, branch/link, branch/link, branch/link, branch/link, branch/link, and branch/link as well as branch only. the maximum number of programmable branch targets is eight.